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Thursday, September 20, 2018

Performance / Resource Divider Generator v5.1 Utilization.

Performance and Resource Utilization for Divider Generator v5.1

Vivado Design Suite Release 2018.2

Interpreting the results:

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case.

The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters.

Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.












  • Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
  • The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
  • Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
  • Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
  • LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
  • Default Vivado Design Suite 2018.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 241 441 230 7 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 396 593 1208 569 13 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 396 901 1827 858 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 797 267 101 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 374 17 127 17 2 3 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 450 1280 3334 1252 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 636 131 262 119 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 494 119 207 97 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 555 64 134 57 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 223 441 210 7 0 1 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 456 548 1208 525 13 0 1 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 456 847 1827 818 16 0 1 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 90 763 267 93 16 0 1 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 424 18 127 18 2 3 0 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 424 1279 3334 1261 0 0 0 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 631 131 262 119 0 0 0 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 511 124 207 99 0 0 0 PRODUCTION 1.25.01 01-12-2017
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 604 68 134 61 0 0 0 PRODUCTION 1.25.01 01-12-2017

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 224 441 212 7 0 1 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 571 573 1208 550 13 0 1 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 571 865 1827 835 16 0 1 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 119 760 267 88 16 0 1 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 615 18 127 18 2 3 0 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 800 1279 3334 1248 0 0 0 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 872 129 262 121 0 0 0 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 779 125 207 109 0 0 0 PRODUCTION 1.20 05-21-2018
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 872 67 134 63 0 0 0 PRODUCTION 1.20 05-21-2018

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 243 441 230 7 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 396 593 1208 567 13 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 396 901 1827 858 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 818 267 105 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 374 17 127 17 2 3 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 461 1280 3334 1248 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 636 129 262 117 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 483 119 207 100 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 516 64 134 57 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 221 441 208 7 0 1 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 456 549 1208 525 13 0 1 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 456 848 1827 817 16 0 1 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 90 754 267 97 16 0 1 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 424 18 127 18 2 3 0 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 472 1276 3334 1254 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 658 130 262 118 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 544 125 207 97 0 0 0 PRODUCTION 1.26.01 01-12-2017
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 610 68 134 62 0 0 0 PRODUCTION 1.26.01 01-12-2017

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 223 441 213 7 0 1 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 571 574 1208 549 13 0 1 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 571 866 1827 835 16 0 1 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 119 765 267 90 16 0 1 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 615 18 127 18 2 3 0 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 642 1279 3334 1238 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 872 130 262 120 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 763 124 207 104 0 0 0 PRODUCTION 1.20 05-21-2018
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 839 68 134 63 0 0 0 PRODUCTION 1.20 05-21-2018

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 222 441 209 7 0 1 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic
aclk 571 573 1208 550 13 0 1 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic
aclk 571 866 1827 835 16 0 1 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 119 752 267 94 16 0 1 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic
aclk 615 18 127 18 2 3 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic
aclk 790 1279 3334 1244 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic
aclk 872 131 262 120 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic
aclk 828 123 207 100 0 0 0 PRODUCTION 1.20 05-21-2018
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic
aclk 872 68 134 62 0 0 0 PRODUCTION 1.20 05-21-2018

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Copyright 2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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