CryptoURANUS Economics


Wednesday, July 24, 2019

Transaction-output: Cryptocurrency

Transaction output

In the context of Bitcoin in reference of an output contains instructions for sending bitcoins.

In this value is the number of Satoshi (1 BTC = 100,000,000 Satoshi) that this output will be worth when claimed.

For more information about "Transaction output", see this external article.

See also: Change address, Transaction, Transaction input
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Transaction-input: Cryptocurrency

Transaction input

Transaction input In the context of Bitcoin is an input that is a reference to an output from a previous transaction.

Multiple inputs are often listed in a transaction.

An input can only be spent as a whole.

If payment is smaller than the input, the remaining change is sent back to the user's change address.

For more information, see this external article.

Making cryptocurrency user(s) experience easier, Trezor Wallet calculates all the inputs and outputs and displays only the final balances and transaction amounts.

Detailed information of the Trezor Wallet and transactions, see Transaction details.

See also: Change address, Transaction, Transaction output

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Lightning-Network: Cryptocurrency

Lightning Network

The Lightning Network is an off-chain approach for solving Bitcoin scalability issues.

It is a proposed implementation, "Hashed Timelock Contracts" (HTLCs), with bi-directional payment channels which allows payments to be securely routed across multiple peer-to-peer payment channels.

This architecture of payment channels permits network formation within any peer on the network that can pay any other peer even if they do not directly have a channel open between each other which speeds up process quickly.

A prerequisite for Lightning network is enabling SegWit which solved the malleability issue (BIP141 - Segregated Witness - Consensus layer: This BIP enabled SegWit as a soft-fork in Bitcoin.

It is also prerequisite for Lightning network as it solves malleability issue of pre-segwit transaction types.

In particular, BIP141 defines the following new transaction type: P2WPKH, P2WPKH-in-P2SH, P2WSH, P2WSH-in-P2SH, where only the first two types are currently supported in Trezor.  See also: BIP141 source).

Key features of the Lightning network are:
  • Rapid payments
  • No third-party trust
  • Reduced blockchain load
  • Channels can stay open indefinitely
  • Rapid cooperative closes
  • Outsourceable enforcement
  • Onion-style routing
  • Securely cross blockchains
  • Multisignature capable
  • Sub-satoshi payments
  • Single-funded channels
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Bech32: Cryptocurrency


Bech32 is a SegWit address format specified by BIP173, (BIP173 - Base32 address format for native v0-16 witness outputs This BIP proposes a new format for native SegWit addresses, called Bech32.)

BIP173 - Base32 is currently not supported in Trezor Wallet, although it is supported in Trezor.

See also: BIP173 source.

This address format is also known as "bc1 addresses".

Main disadvantages of base58 format which has been used in Bitcoin for most of its history are:
  • Base58 needs more visible space in QR codes image. Base58 cannot use the alphanumeric mode.
  • The mixed case in base58 makes it inconvenient to reliably write down, type on mobile keyboards, or read out loud.
  • The double SHA-256 checksum is slow and has no error-detection guarantees.
  • Most of the research on error-detecting codes only applies to character-set sizes that are a prime power, which 58 is not.
  • Base58 decoding is complicated and relatively slow.
A Bech32 string is at most 90 characters long and consists of:
  • The human-readable part.
    • "bc" for mainnet
    • "tb" for testnet
  • The separator, which is always "1".
  • The data part, which is at least 6 characters long and only consists of alphanumeric characters excluding "1", "b", "i" and "o".

Trezor with Bech32 addresses

Trezor already implemented Bech32 addresses in its firmware, it is possible to send funds to Bech32 addresses using Trezor Wallet. Receiving is possible using Electrum with native segwit (P2WPKH) option.
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SHA-256 Hash-Algorithm: Cryptocurrency


SHA-256 (Secure Hash Algorithm) is a cryptographic hash (sometimes called ‘digest’).

SHA-256 is a member of the SHA-2 cryptographic hash functions designed by the NSAgov.

Cryptographic hash functions are mathematical operations run on digital data, SHA-256 generates an almost-unique 256-bit (32-byte) signature.

By comparing the computed "hash", (the output from execution of the algorithm), to a known and expected hash value, a person can determine the data's integrity.

A one-way hash can be generated from any piece of data, but the data cannot be generated from the hash. 
Example: 'ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad' 
is a SHA-256 hash for text 'abc'

See also Trezor Cryptography

SHA-256 in Bitcoin

SHA-256 is used in several different parts of the Bitcoin network:
  • Mining uses SHA-256 as the Proof-of-work algorithm.
  • SHA-256 is used in the creation of bitcoin addresses to improve security and privacy.
SHA-256 in Trezor
SHA-256 is used in Recovery seed creation.

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QR-Code: Cryptocurrency

QR code

A QR code, or Quick Response Code, is a two-dimensional machine-readable barcode that can be used to represent an address. The use of a QR code makes it easy to scan an address, rather than having to type or copy it.

Why to use a QR code

When using Bitcoin, and alt.coin cryptocurrencies for point-of-sale or face-to-face transaction solidifies the problem how to communicate the receiving address the person paying can use. A Bitcoin address is between 27 and 34 characters long. This takes time to type manually, and it is easy to make a mistake.

On the other hand, a QR code can quickly and reliably amount of data in a machine-readable manner.

The QR code can (potentially) contain other information as well, such as an amount and a message.
With a mobile phone, a convenient way to pass that data is for the payment recipient (e.g., a merchant) to display a QR code with the Bitcoin address for the transaction, and then for the person paying to scan that code to obtain the address.

It is also possible to print out the QR code containing the user's receiving address and hand it to the sender, who can use it for repeated or regular payments.

How does a QR code work

As mentioned above, a QR code is a two-dimensional barcode that contains machine-readable information in a convenient manner. It was first designed in 1994 for the automotive industry in Japan and has since expanded to a wide range of applications. Where a traditional barcode presents a string of information as a one-dimensional line of black and white bars, a two-dimensional barcode packs significantly more information into a grid of black and white squares.
It contains the following information:
  1. Quiet zone: The empty white border is making it possible to identify the code among other printed information.
  2. Finder patterns: Larger black and white squares in three of the corners. They differentiate QR codes from other types of barcodes and make the orientation of the code clear.
  3. Alignment pattern: Ensures the code can be deciphered even if the code is distorted.
  4. Timing pattern: Makes it easy to identify the individual data cells within a QR code and is especially useful when the code is damaged or distorted.
  5. Version information: Identifies the specific standard of the QR code.
  6. Data cells: Contain some of the actual data in the code.

To understand how transactions work on basic technical level, check blog post Types of Bitcoin transactions: Part I, Part 2.

More detailed description can be found in Bitcoin Wiki or in Developer guide.
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Tuesday, July 23, 2019

Offload CPU-2-FPGA DataCenters: Cryptocurrency

Offload CPU-2-FPGA DataCenters

FPGA-Based Host CPU Offload with Industry-Standard Data Center Server

By Ameet Dhillon, Director of Business Development, Accolade Technology


We are all familiar with the term “industry-standard” or “commercial off-the-shelf (COTS)” servers. The generally accepted understanding is these are servers which contain readily available components such as an x86 CPU, memory, storage, networking and a ubiquitous operating system such as Linux or Windows.

We usually think of companies like Dell or HP as suppliers of these industry-standard servers, and over time have come to accept that the best platform for our datacenter applications is an industry-standard server. This is certainly true for a large percentage of applications, but we shouldn’t automatically assume there are no other options.

A slight twist to the industry-standard server, which still includes all the standard components, would be the addition of an onboard FPGA. I don’t mean an FPGA as a “bolt-on” in the form of a PCIe adapter/NIC (though that is a valid solution as well), but rather an FPGA that is mounted onto the motherboard and wired up to interact with the various components around it. Just like all the other components, the FPGA performs a specific and vital function; namely host CPU offload.
An FPGA is a programmable device well-suited to performing application specific functions or algorithms. These functions run the gamut from something very specific such as a proprietary security algorithm to more generic requirements such as time stamping, packet filtering or data deduplication.

A repetitive and CPU intensive task is the ideal candidate for offload to an FPGA. It is not uncommon to reduce CPU load by over 50 percent with the help of an FPGA. In addition, FPGA offload enables remarkable scaling of data center applications previously restricted by CPU bottlenecks.

While the benefits of an onboard or “native” FPGA can be very compelling, there are at least two potential downsides to keep in mind. The first is simply cost. Integrating an FPGA can add a relatively significant cost to the server.

However, the return on investment (ROI) is usually quite apparent if your data center application performs repetitive tasks which can be offloaded. Since FPGA offload dramatically reduces the burden on your host CPUs, thereby optimizing application performance, these added benefits are often well worth the cost.
The second downside is FPGA programming complexity. In the FPGA world, you don’t call someone a programmer but rather a “designer” or “design engineer.” This is because FPGAs are not programmed in common languages such as C or Java.

Rather, FPGAs are designed using Verilog or VHDL which are hardware description languages (HDLs) used to model electronic systems. For this reason, it is often not possible for a software application development team to program an FPGA with the specific offload function or algorithm they need to achieve the desired level of CPU offload.

 The solution to this dilemma is to partner with a vendor that has expertise in FPGA design and can provide comprehensive offload functions as well as custom features tailored for each specific customer scenario.
Accolade Technology is a vendor that fits such a profile with its ATLAS-1000 FPGA integrated platform.  

Figure 1 shows the 1U, half-width, ATLAS-1000 incorporating a Xilinx FPGA natively on the motherboard.

Like industry-standard servers, the ATLAS-1000 provides a multi-core Intel CPU, memory and storage along with an FPGA loaded with packet processing capabilities such as lossless packet capture, packet filtering, nanosecond precision timestamping, deduplication, flow classification and multi-core DMA.

In addition to the onboard FPGA, the platform has several other unique attributes such as direct GPS decode on the motherboard, pluggable interface modules that support 10 or 40G and a small footprint that accommodates two ATLAS-1000 units mounted side-by-side in a standard 19-inch rack.

Figure 2 shows a comprehensive architectural layout of this hardened platform. The platform is ideal for network/cyber security or monitoring applications such as DPI, NetFlow exporting, data deduplication or cluster load balancing.

For Website Source of details visit this link.