10 Ways To Program Your FPGA
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Despite the recent push toward high level synthesis (HLS), hardware description languages (HDLs) remain king in field programmable gate array (FPGA) development. Specifically, two FPGA design languages have been used by most developers: VHDL and Verilog. Both of these “standard” HDLs emerged in the 1980s, initially intended only to describe and simulate the behavior of the circuit, not implement it.
However, if you can describe and simulate, it’s not long before you want to turn those descriptions into physical gates.
For the last 20 plus years most designs have been developed using one or the other of these languages, with some quite nasty and costly language wars fought. Other options rather than these two languages exist for programming your FPGA. Let’s take a look at what other tools we can use.
C / C++ / System C
The C, C++ or System C option allows us to leverage the capabilities of the largest devices while still achieving a semblance of a realistic development schedule... although that may just be my engineering management side coming out.
The ability to use C-based languages for FPGA design is brought about by HLS (high level synthesis), which has been on the verge of a breakthrough now for many years with tools like Handle-C and so on. Recently it has become a reality with both major vendors, Altera and Xilinx offering HLS within their toolsets Spectra-Q and Vivado HLx respectively.
A number of other C-based implementations are available, such as OpenCL which is designed for software engineers who want to achieve performance boosts by using a FPGA without a deep understanding of FPGA design. Whereas HLS is still very much in the area of FPGA engineers who want to increase productivity.
As with HDL, HLS has limitations when using C-based approaches, just like with traditional HDL you have to work with a subset of the language. For instance, it is difficult to synthesize and implement system calls, and we have to make sure everything is bounded and of a fixed size.
What is nice about HLS, however, is the ability to develop your algorithms in floating point and let the HLS tool address the floating- to fixed-point conversion.
As with many things, we are still at the start of the journey: I am sure over the coming years, we will see HLS increasingly used in different languages, making HLS similar to very low level of a software engineer’s C.
More info:
10 FPGA dev tools:
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FPGA software 1 - FPGA design software
- Design-entry.
- Simulation.
- Synthesis / place-and-route.
- Programming through special cables (JTAG).
- Xilinx's free software is named ISE WebPACK, which is a scaled-down version of the full ISE software.
- Altera's free software is named Quartus Web/Lite Edition, which is a scaled-down version of the full Quartus II software.
Here's a summary of the features/limitations of the software:
| Design-entry | VHDL, Verilog, ABEL, Schematic, EDIF | VHDL, Verilog, SystemVerilog, AHDL, Schematic, EDIF |
|---|---|---|
| Core generator | Yes (CORE Generator) | Yes (MegaWizard Plug-Ins) |
| Functional simulation | No | No (last version with simulation was 9.1SP2) |
| Testbench simulation | Use ISim | Use ModelSim-Altera Starter Edition |
| Synthesis/P&R | Free version limited to small & medium devices | Free version limited to small & medium devices |
| Programming | Yes | Yes |
| FPGA editor | Yes (FPGA editor) | Yes (Chip Editor) |
| Embedded logic analyzer | ChipScope PRO (a separate product - not free) | SignalTap II (included in Quartus II Web/Lite edition) |
| Older versions | Available from ISE Classics | Available from the Quartus II Software Archive |
| OS support | Windows + Linux | Windows + Linux |
| Price | Free version: $0 Full version: starting at $2995 for a 12 month license | Free version: $0 Full version: $2995 for a 12 month license |
| Software matrix | Check here | Check here |
Which is better?
As of this writing (May 2013), Quartus-II is better overall - it runs faster, has a better GUI, better HDL support and includes one killer feature: SignalTap II embedded logic analyzer, which is easy to use and available in the free edition. Altera's low point is their simulator - they dropped their own integrated simulator but didn't have anything to replace it so rely on ModelSim for now.ISE is pretty good overall. Its low points are basic HDL support and ChipScope PRO (not part of the free suite).
Xilinx has a new software suite called Vivado but limited to high-end devices.
Xilinx traditionally had better silicon, and Altera better software... this seems to still hold true.
OpenCores: EDA Tools
Introduction
OpenCores is the world largest community focusing on open source development targeted for hardware. Designing IP cores, is unfortunately not as simple as writing a C program. A lot more steps are needed to verify the cores and to ensure they can be synthesized to different FPGA architectures and various standard cell libraries.Open Source EDA tools
There are plenty of good EDA tools that are open source available. The use of such tools makes it easier to collaborate at the opencores site. An IP that has readily available scripts for an open source HDL simulator makes it easier for an other person to verify and possibly update that particular core. A test environment that is built for a commercial simulator that only a limited number of people have access to makes verification more complicated.Icarus Verilog Simulator
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the &qout;vvp&qout; command. For synthesis, the compiler generates netlists in the desired format.The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005.
Icarus web site
Verilator
Verilator is a free Verilog HDL simulator. It compiles synthesizable Verilog into an executable format and wraps it into a SystemC model. Internally a two-stage model is used. The resulting model executes about 10 times faster than standalone SystemC.Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. Therefor we have chosen this tool to be used in the verification environment for the OpenRISC processor.
Verilator web site
GHDL VHDL simulator
GHDL implements the VHDL87 (common name for IEEE 1076-1987) standard, the VHDL93 standard (aka IEEE 1076-1993) and the protected types of VHDL00 (aka IEEE 1076a or IEEE 1076-2000). The VHDL version can be selected with a command line option.GHDL web site
EMACS - text editor
GNU Emacs is an extensible, customizable text editor—and more.Very good support for both Verilog HDL and VHDL editing.
Emacs web site
Fizzim is a FREE, open-source GUI-based FSM design tool
The GUI is written in java for portability. The backend code generation is written in perl for portability and ease of modification.Features:
GUI:
- Runs on Windows, Linux, Apple, anything with java.
- Familiar Windows look-and-feel.
- Visibility (on/off/only-non-default) and color control on data and comment fields.
- Multiple pages for complex state machines.
- "Output to clipboard" makes it easy to pull the state diagram into your documentation.
Backend:
- Verilog code generation based on recommendations from experts in the field.
- Output code has "hand-coded" look-and-feel (no tasks, functions, etc).
- Switch between highly encoded or onehot output without changing the source.
- Registered outputs can be specified to be included as state bits, or pulled out as independent flops.
- Mealy and Moore outputs available.
- Transition priority available.
- Automatic grey coding available.
- Code and/or comments can be inserted at strategic places in the output - no need to "perl" the output to add your copyright or `include
TCE
TCE is a toolset for designing application-specific processors (ASP) based on the Transport triggered architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.TCE has been developed internally in the Tampere University of Technology since the early 2003. The current source code base consists of roughly 400 000 lines of C++ code.
TCE web site
C to Verilog translation
Available is an online C to Verilog compiler. The code generated by the site is licensed under BSD (use it "as is").C-to-Verilog web site
Fedora Electronic Lab
Fedora Electronic Lab tries to provide a complete hardware design flow with the best opensource tools. We try to ensure interoperability as far as we can and we work with other opensource developers to improve existing EDA tools.Fedora Electronic Lab web site
Linux - The logical choice for EDA
Subproject Teams:AIRE ImplementationFrontend -parser/analyzer/codegen Simulator Debugger Waveform Viewer Testing/compliance LinksRelated Projects...Commercial EDA software for Linux Press Subscribe to mailing listMailing list archivesDownload | A project to develop a free, open source, GPL'ed VHDL simulator for Linux!Project goals: To develop a VHDL simulator that:
FreeHDL is used by Qucs for digital simulation. Qucs is a circuit simulator with graphical user interface. Qucs aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Transient, Noise and Harmonic Balance analysis. It is available from http://sourceforge.net/projects/qucs. Download: Release 0.0.7 of the FreeHDL compiler/simulater system can be downloaded from here. Release 0.0.6 of the FreeHDL compiler/simulater system can be downloaded from here. Release 0.0.5 of the FreeHDL compiler/simulater system can be downloaded from here. |
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