CryptoURANUS Economics

Anti-AdBlocker

Saturday, August 24, 2019

Zcoin: Defined in CryptoCurrency

Zcoin:
Defined in CryptoCurrency


Zcoin (XZC) is an open-source privacy-focused cryptocurrency token that launched in Sep 2016. To enable privacy, Zcoin uses zero-knowledge proofs via the Zerocoin protocol.



Zerocoin is a cryptocurrency proposed by Johns Hopkins University professor Matthew D. Green and graduate students Ian Miers and Christina Garman as an extension to the Bitcoin protocol that would add cryptographic anonymity to Bitcoin transactions.

With Zcoin’s Zerocoin feature, only the sender and receive would be able to ascertain the exchange of funds in a given transaction, as no transaction histories are linked to the actual coins. Zcoin operates a multi-node model where mining nodes verify blockchain transactions and Znodes store blockchain data.

Privacy-enhancing Technology, Zerocoin Protocol Zero-Knowledge Cryptographic Proofs.

In Bitcoin, all transactions are broadcasted on a public ledger. Research has shown that external information, such as publicly announced addresses, can be used to link identities and organizations to transactions. The default reuse of bitcoin addresses exacerbates this problem. 

Furthermore, the same type of mechanism used to break privacy in social networks, such as the analysis of social network topology, can be used to break privacy in the Bitcoin network.
 

Bitcoin and preceding alternative cryptocurrencies attempted to solve this problem through the use of transaction mixers or ring signatures.

However, there are a number of drawbacks to these proposed solutions. For one, a malicious or compromised member of a mixer and-or ring signature can break privacy the transaction mixer.

Furthermore, the anonymity set is a key metric to understanding how private a cryptocurrency is.  The anonymity set in formerly proposed solutions is limited by the size of the mixing cycle and-or ring signature.


Each mixing cycle and-or ring signature is limited by the number of transactions per cycle, which is transitively limited by the the block size of the cryptocurrency.

Thus, the anonymity set in previous attempts at privacy tends to only be a few hundred transactions.

With Zcoin, the anonymity set is on a dramatically higher magnitude. Instead of having an anonymity set limited to the few dozen, Zcoin has an anonymity set that encompasses all minted coins in a particular RSA accumulator that can scale to many thousands and unlike other solutions is not subject to transaction graph analysis.

Wednesday, August 21, 2019

Generate Bitstream, Program FPGA Free


Generate Bitstream, Program FPGA Free

OptEditorial/Reference:


Reference:
Xilinx always Answers Question, but intel forums rarely do: -i.e. is/are/will any Xilinx bitstream file(s) can be generated with Xilinx free license?


With a Xilinx board you will get a Device-Locked license for the Xilinx software tools (typically Vivado) as described by AR#39845.



Ans For: AR#39845

AR# 39845
Licensing - What does a device locked license allow?

Description A device locked license is usually included with purchased kits and boards (for example SP605, VC707. etc...).

What does this type of license allow?

Is it possible to use the full ISIM and ChipScope Pro tool with access to other devices?

Solution A device locked license typically includes the following features.


Increment Web_Package which gives access to PlanAhead and WebPACK software implementation for WebPACK devices.


Increment "Specific Device" which provides additional access to implementation for the locked device.

Increment "Design Edition" (Logic Edition, Embedded Edition, DSP Edition depending on the board) which allows access to other design tools.

The device license allows for synthesis and implementation of a design targeted to that specific device.

Bitstream generation is also allowed as long at the device in question is not considered early access in the software version being used.

A device locked license covers all the packages of a device.




For example:
The SP605 Evaluation Kit includes a full-seat of Xilinx ISE Design Suite: Logic Edition device locked to the Spartan-6 XC6SLX45T device.



It allows you access to ISE, PlanAhead, ISIM and ChipScope Pro tools for XC6SLX45T as well as WebPACK devices.

The Xilinx tools allow you to enter your design using HDL (eg. VHDL or Verilog), generate a bitstream, and download the bitstream to the FPGA via JTAG or to a flash-memory device connected to the FPGA via JTAG.

If you are making your own FPGA board, then Xilinx offers a free WebPack version of the tools that supports many of the Xilinx FPGAs.

For example, the WebPack Vivado tools support the many Xilinx FPGAs.

Here, shown in Table-1 of Xilinx document UG973 as reference.



That is, WebPack Vivado allows you to enter a design using HDL, generate a bitstream, and download the bitstream to the supported FPGAs and flash-memory.





Monday, August 12, 2019

How to learn to code | Computer Programming




How to learn to code | Computer Programming




TechLead / Published on Jun 9, 2018
Ex-Google tech lead Patrick Shyu explains how to learn to code quickly and easily, with this one weird trick! 
It's so simple with this 1-step program! Are you looking to hack into the mainframe, bypassing the system security lock to gain root access into the private kernel? 
Well, if I can do it, so can you! * ABOUT SITTING: It is highly unhealthy to sit for long periods of time. 
I always get up and take a short break every 30 minutes. 
Note though that even with breaks, it is known that long periods of general inactivity will put your body to sleep and you need to take longer walks/jogs throughout the day to keep up a healthy metabolism. 
Take care of your back/neck posture as well. 
http://youtube.com/techlead?sub_confi... ► Preparing for Technical Interviews? 
Join me in my new coding interview training program: http://techinterviewpro.com/ ► 
Join me for daily coding interview practice: http://dailyinterviewpro.com/ ► 
For more tech career & interview tips & tricks, check out TechLead: 
Season 1 Complete HD available for purchase. http://www.techseries.dev/season1 ► 
Check the tech & camera gear that I'm using (★★★★★): http://amazon.com/shop/techlead ► 
Get extra whiteboard coding practice at: http://algoexpert.io/techlead Use code "techlead" for a discount, ends soon! ► 


How To Program an FPGA With Xilinx ISE Webpack In Verilog or VHDL




How To Program an FPGA With Xilinx ISE Webpack In Verilog or VHDL


A Basys2 tutorial. Learn to use Xilinx's ISE Webpack and Digilent's Adept to upload code to your Basys 2 FPGA. In this tutorial we will walk you step by step from downloading all the way to programming a Basys2 FPGA. 

Software needed links: Digilent Adept: https://www.digilentinc.com/Products/... 


Digilent Basys2 Board Reference Manual: https://www.digilentinc.com/Data/Prod... 

 Basys™2 Spartan-3E FPGA Board: https://www.digilentinc.com/Products/... 

Learning Resources: Book To Learn Verilog: Verilog HDL http://www.amazon.com/gp/product/0132... 

Book To Learn Logic Design: Fundamentals of Logic Design http://www.amazon.com/gp/product/0495... 

Book To learn Verilog or VHDL and Logic Design at a fast pace, with not a lot of detail: Introduction to Digital Design http://www.digilentinc.com/Products/D... 

Website Resources: http://www.fpga4fun.com/
Category


Sunday, July 28, 2019

Designing FPGA Tutorial

Designing FPGA Tutorial



New Horizons


image


Welcome to Sven Andersson's blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company...

 Content
New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



Friday, July 26, 2019

CryptoMining via FPGA



CryptoMining via FPGA's:







FPGA for Dummies & Experts Alike!


The ASICs had overtaking GPU mining, but an alternative to ASIC mining was born. 

The new wolfpack leader appears as the Field Programmable Gate Arrays, or shortly FPGA and it is taking over very fast.

The only issue here is the boards are difficult to find each passing month.

Disclaimer: this post is not sponsored by any company nor have any referral links.

 

Let’s look at why FPGA is interesting for mining.

The Two Main Issues FPGA Are Meant to Solve Cryptocurrencies are volatile and unstable in the current market, August-2018. 

 

Cryptocurrency market have been jumping from Ethereum to Monero to Zcash, back and forth, depending on the volatility of coin profitability. 

The ASICs storming the mining pool strategy is to buy an ASIC miner and pray that it pays off in time. GPU mining  and the amount of coins you can mine is limited and people find this unsatisfactory 75% of the time.

The ASIC's issue is it offers zero flexibility when it comes to a single coin that can be mined and no other type of cryptocurrency coin. 

 

An ASIC is hard-wired to mine one algorithm type of coin only. 



Highest End, Lowest Cost:

Ultra96 is an Arm-based, Xilinx Zynq UltraScale+ MPSoC development board based on the Linaro 96Boards specification. 

The 96Boards’ specifications are open and define a standard board layout for development platforms that can be used by software application, hardware device, kernel, and other system software developers. 

 

Ultra96 represents a unique position in the 96Boards community with a wide range of potential peripherals and acceleration engines in the programmable logic that is not available from other offerings. 

Ultra96 boots from the provided Delkin 16 GB MicroSD card, pre-loaded with PetaLinux. 

 

Engineers have options of connecting to Ultra96 through a Webserver using integrated wireless access point capability or to use the provided PetaLinux desktop environment which can be viewed on the integrated Mini DisplayPort video output. 

 

Multiple application examples and on-board development options are provided as examples. 

 


Ultra96 provides four user-controllable LEDs. 

 

Engineers may also interact with the board through the 96Boards-compatible low-speed and high-speed expansion connectors by adding peripheral accessories such as those included in Seeed Studio’s Grove Starter Kit for 96Boards. 

 

Micron LPDDR4 memory provides 2 GB of RAM in a 512M x 32 configuration. Wireless options include 802.11b/g/n Wi-Fi and Bluetooth 4.2 (provides both Bluetooth Classic and Low Energy (BLE)). 

 

UARTs are accessible on a header as well as through the expansion connector. JTAG is available through a header (external USB-JTAG required). I2C is available through the expansion connector. 

 

 Ultra96 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided on the high speed expansion bus. 

 

Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub are specified. 

 

 The integrated power supply generates all on-board voltages from an external 12V supply (available as an accessory).



What’s the Third Option: There is always other option$. 

 

FPGA is the hardware taking over the market by storm. This is the new favorite in the cryptocurency mining community. 

 

FPGA have been around since 1979. 

 

They heavily used in science, vehicle modeling and even military deployment applications.

 

The first manufacturer of these devices is an American technology company called "Xilinx"

 

Years followed and another American company called Altera, (now owned by Intel), has joined the industry and has been the main Xilinx competitor since then.

 

The development of FPGA circuitboards have been welcomed very in many industries and the demand FPGA hardware technology is still booming. 

In 2013, the market for FPGA circuit boards was $6.1 billion and estimated $21.3 billion by year 2020.



Why FPGA Have not been used in cryptocurrency mining:

Since Bitcoin became popular, average people tried to mine with FPGA, but failed because they did not have the programming skill sets to utilize the FPGA circuit-boards.

 

The only people have mined FPGA circuit-boards were large mining exchanges, and they kept the FPGA circuit boards a secret for years.

 

When the first open source FPGA Bitcoin miner was released from private sectors until May 20, 2011. 




Juan Antonio Ernesto's Great Adventure:

A man named Juan Antonio Ernesto's, [his named was changed here to protect his immigration innocence], from Tijuana Mexico, who illegally migrated into Canada from Mexico, and was hired by Canada's silicon-valley, (in Waterloo Ontario).

After three years Juan left Canada, because of bias Canadian in that country, so Juan Antonio said, he had to leave to U.S..

When Juan entered the U.S. he was immediately granted citizenship by the U.S. government, because enrolled into U.S. college for free and acquired his CS-masters degree from NMT Socorro New-Mexico under his real name.

While he was in Socorro NM he and other Mexicans-Americans secretly managed the cryptocurrency mining software exchanged named "Macho-Rio-Grande".

The Mexican trio enabled the FPGA Xilinux cards workable and online usable for cryptocurrency mining.

The trio secretly made millions of dollars and they were the only private-public sector aware of this technology.

When Juan returned with millions of dollars of wealth to share with his friends in Canada he died from a fatal gunshot wound by MS13 in Vancouver Canada on the highway of tears.

Juan's bank accounts and cryptocurrencies was transferred before his death never to be found again.

Juan's friends ran to Mexico with the FPGA software technology and where also found dead months later and their accounts where all transferred the same.

All deaths related to these events where determined suicide, and the mystery of their deaths continues as everyone suspects MS13 hackers.

NOW, there are three reasons why FPGA circuit-boards have never really made it to the masses until today and the above mentioned is the first.

The Reason #1, is the lacking of non-programmable flexibility and software to architecture specifics. 

FPGA boards are not easy to software program, and they can be programmed to mine cryptocurrency. 

In order to use a FPGA board you must have hardware and software programming abilities.

The GPU works differently and the only changes enabled is to tweak the clock speed, and mining software.

The FPGA circuit-board has got to be programmed in raw-code from scratch in order to mine cryptocurrency. Writing the code in Verilog or VHDL language -and– neither Python nor C++ works, but only Verilog or VHDL languages.

Only dedicated programmers are capable managing this task from beginning equation to end resolved solution.

The Reason #2, is the creation of the first ASIC for mining cryptocurrencies, Unlike FPGA, was an ASIC hard-coded as a plug and play hardware only and not reprogrammable. 

Anyone can use an ASIC Miner-Box. There were a lot of alternatives to ASIC mining-box. Computer programmers have had the option of the GPU rigs and resolved into mining lesser coins than an FPGA circuit-board capable of.

The ASIC miner-box's are dominating the mining pools and Personal Computer Graphic Card GPU's are now less used technology.

The FPGA are becoming the average miner hardware these days.

There are several reasons FPGA are way faster. 


The FPGA circuit-board cards perform 3x to 100x times more efficient than GPU while having the same wattage power voltage draw saving hundred$

Depending on the algorithm matched to bitcoin, FPGA never fall behind ASICs miner-box's.

Upsides of FPGA

+ Compatibility for all mining currencies provided you are a  flexibility with Verilog or VHDL programming languages, or have partnered up with a programmer regards all cryptocurrency mining algorithms. There are no soft-forks affecting mining operations provided the programmer updates FPGA bitstream.

+ Extreme power efficiency compared to CPU's and GPUs.

Downsides of FPGA

+ FPGA have to be plugged into operational computers, just like GPUs.

+ Xilinux Vertex FPGA available to the mainstream for now (there are some exceptions though, which is why this article exists, more on that below).

+ Are quite pricey compared to GPUs.

+ Can be slightly outperformed by ASICs depending on the algorithm.

Bitstream:

The Bitstream is the program written on a low-level programming language known as Verilog or VHDL that tells the FPGA what to do.

If you want to mine a specific algorithm you must have a bitstream that tells the FPGA how to mine that specific algo.

Bitstreams are loaded to the FPGA once the system boots. The bitstream is loaded into the volatile FPGA RAM memory. This is the same DDR4 memory – the FPGA model people use for mining has got 64GB of it. 

This huge amount of RAM allows the FPGA to store hundreds of bitstreams and switch between those in fractions of a second.

This functionality allows an FPGA to mine algorithms such as Timetravel10, X11Evo, X16R and X16S that require the chip to switch between various “lesser” hashing algorithms every few minutes.

While the bitstream can be changed in a fraction of a second, the board can still mine only one algorithm at a time with a couple rare exceptions.

Anyone can create bitstreams for existing mining algos and Zetheron (name of the company) will be collecting a fixed fee on behalf of the developers. This will ensure:

  • safety to the developers of bitstreams – they will get paid for their work and

  • no entry fee for FPGA owners – you pay only if the bitstream you have downloaded works

  • Plus, the access to a diversity of community-made bitstream will certainly guarantee that we will be able to mine virtually any algo and fork we want.

As for today, Zethereon has working bitstream for Cryptonote and Lyra2z algos. “The current plan is to release approximately one algorithm per month, until all major algorithms in the above table have been covered.”  – Zetheron writes. Here is a table of all the planned coins for the VU9P FPGA.

This means that thanks to the work those guys did, we will now have a seamless, pretty much plug-and-play experience when using our FPGA boards.

The ecosystem Zetheron is creating will give us all the bitstream solutions we need to mine any popular algorithm we want without the need to know anything about programming. Plus, developers will be motivated to push the plank higher and create better bitstreams.



 




 

Ultra96 Monero Miner



Ultra96: Defined




Avnet Ultra96
Price: $249
Part Number: AES-ULTRA96-G
Device Support:
Zynq UltraScale+ MPSoC
 Vendor: Avnet
The Future is AVNET...

Program Tier:

  1. Premier
  2. View Partner Profile


Product Description:

Ultra96™ is an ARM-based, Xilinx Zynq UltraScale+™ MPSoC development board based on the Linaro 96Boards specification. The 96Boards’ specifications are open and define a standard board layout for development platforms that can be used by software application, hardware device, kernel, and other system software developers. Ultra96 represents a unique position in the 96Boards community with a wide range of potential peripherals and acceleration engines in the programmable logic that is not available from other offerings.

Key Features and Benefits:

  • Linaro 96Boards Consumer Edition compatible
  • 85mm x 54mm form factor
  • 60-pin 96Boards High speed expansion header
  • 40-pin 96Boards Low-speed expansion header
  • 2x USB 3.0, 1x USB 2.0 Type A downstream ports
  • 1x USB 3.0 Type Micro-B upstream port
  • Mini DisplayPort (MiniDP or mDP)
  • Wi-Fi / Bluetooth
  • Delkin 16 GB MicroSD card + adapter
  • Micron 2 GB (512M x32) LPDDR4 Memory
  • Xilinx Zynq UltraScale+ MPSoC ZU3EG A484

What's Included:

  • 16 GB pre-loaded microSD card + adapter
  • Quick-start instruction card
  • Ultra96 development board
  • Voucher for SDSoC license from Xilinx
==================






















About:

  • The Ultra96 is the Arm-based, Xilinx Zynq UltraScale+ MPSoC development board based on the Linaro 96Boards specification.
  • We sat down with Robert Wolff and Sahaj Sarup from the 96Boards team within Linaro, to talk about the new Ultra96 FPGA board.
  • This powerful, adaptable single-board computer runs PetaLinux, and is perfect for flexible application development within image processing, AI, and more.

http://zedboard.org/product/ultra96
http://96boards.org
http://linaro.org
Part 2: Demos – https://youtu.be/MoCFhOiGj6c
Part 3: SDSoC – https://youtu.be/pdXdKK14xfo


The 96Boards’ specifications are open and define a standard board layout for development platforms that can be used by software application, hardware device, kernel, and other system software developers.

Ultra96 represents a unique technological position in the 96Boards tier community with a wide range of potential peripherals and acceleration-software engines.



This is all umbrella by the programmable logic that is not available from other offerings other-than the tier group community standardized; CISCO and what you qualify for in consumer sales.

Ultra96 boots from the provided Delkin 16 GB Micro-SD card, pre-loaded with Peta-Linux Operating-System.

Engineers have options of connecting to Ultra96 through an intranet/internal Webserver using integrated wireless access point capability or to use the provided Peta-Linux desktop environment.




The Peta-Linux desktop environment can be viewed on the integrated Mini DisplayPort video output onto a PC and-or MAC hardware monitor interface.

Multiple application examples and on-board development options are provided as examples.

Ultra96 provides novice to professional four user-controllable LEDs.


Engineers may also interact with the board through the 96Boards-compatible low-speed and high-speed expansion connectors by adding peripheral accessories such as those included in Seeed Studio’s Grove Starter Kit for 96Boards.



Micron LPDDR4 memory provides 2 GB of RAM in a 512M x 32 configuration. Wireless options include 802.11b/g/n Wi-Fi and Bluetooth 4.2 (provides both Bluetooth Classic and Low Energy (BLE)). UARTs are accessible on a header as well as through the expansion connector. JTAG is available through a header (external USB-JTAG required). I2C is available through the expansion connector.



Ultra96 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided on the high speed expansion bus. Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub are specified.
The integrated power supply generates all on-board voltages from an external 12V supply (available as an accessory).


 

 Features:

  • Xilinx Zynq UltraScale+ MPSoC ZU3EG SBVA484.
  • Micron 2 GB (512M x32) LPDDR4 Memory.
  • Delkin 16 GB MicroSD card + adapter.
  • Pre-loaded with PetaLinux environment.
  • Wi-Fi / Bluetooth.
  • Mini DisplayPort (MiniDP or mDP).
  • 1x USB 3.0 Type Micro-B upstream port.
  • 2x USB 3.0, 1x USB 2.0 Type A downstream ports.
  • 40-pin 96Boards Low-speed expansion header.
  • 60-pin 96Boards High speed expansion header.
  • 85mm x 54mm form factor.
  • Linaro 96Boards Consumer Edition compatible.

 Target Applications:

  • Artificial Intelligence.
  • Machine Learning.
  • IoT/Cloud connectivity for add-on sensors.

 Optional Add-On Items:

  •  External 2.0A @ 12V power supply
  •  USB-to-JTAG/UART pod (coming soon)
  •  Seeed Studios Grove Starter Kit for 96Boards
  •  Compatible Accessories

 

 Other Qualified microSD Cards:

  •  Delkin Utility MLC 128 GB microSD Card